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1/13 july 2001 n high speed: f max = 60 mhz (typ.) at v cc = 4.5v n low power dissipation: i cc = 4 m a(max.) at t a =25c n compatible with ttl outputs : v ih = 2v (min.) v il = 0.8v (max) n symmetrical output impedance: |i oh | = i ol = 6ma (min) n balanced propagation delays: t plh @ t phl n pin and function compatible with 74 series 646 description the 74hct646 is an advanced high-speed cmos octal bus transceiver and register (3-state) fabricated with silicon gate c 2 mos technology. this device consists of bus transceiver circuits with 3 state, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. data on the a or b bus will be clocked into register on the low to high transition of the appropriate clock pin (clock ab or clock ba). enable (g ) and direction (dir) pins are provided to control the transceiver functions. in the transceiver mode, data present at the high-impedance port may be stored in either register or in both. the select controls (select ab select ba) can multiplex stored and real time (transparent mode) data. the direction control determines which bus will receive data when enable g is active (low). in the isolation mode (enable g high), "a" data may be stored in one register and/or "b" data may be stored in the other register. when an output function is disabled, the input function is still enabled and may be used to store and transmit data. only one of the two buses, a or b, may be driven at a time. all inputs are equipped with protection circuits against static discharge and transient excess voltage. m74hct646 octal bus transceiver/register with 3 state outputs pin connection and iec logic symbols order codes package tube t & r dip m74hct646b1r sop m74hct646m1r M74HCT646RM13TR tssop m74hct646ttr tssop dip sop
m74hct646 2/13 input and output equivalent circuit pin description truth table x : dont care z : high impedance qn : the data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : the data at the a and b bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. pin no symbol name and function 1 clock ab a to b clock input (low to high, edge-triggered) 2 select ab select a to b source input 3 gab direction control input 4, 5, 6, 7, 8, 9, 10, 11 a1 to a8 a data inputs/outputs 20, 19, 18, 17, 16, 15, 14, 13 b1 to b8 b data inputs/outputs 21 g output enable input (active low) 22 select ba select b to a source input 23 clock ba b to a clock input (low to high, edge triggered) 12 gnd ground (0v) 24 v cc positive supply voltage g dir cab cba sab sba a b function hx inputs inputs both the a bus and the b bus are inputs x x x x z z the output functions of the a and b bus are disabled x x inputs inputs both the a and b bus are used for inputs to the internal flip-flops. data at the bus will be stored on low to high transition of the clock inputs. lh inputs outputs the a bus are inputs and the b bus are outputs xx*l x ll the data at the a bus are displayed at the b bus hh x* l x l l the data at the a bus are displayed at the b bus. the data of the a bus are stored to internal flip-flop on low to high transition of the clock pulse hh xx*h x x qn the data stored to the internal flip-flop are displayed at the b bus. x* h x l l the data at the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the b bus. hh ll outputs inputs the b bus are inputs and the a bus are outputs. x* x x l ll the data at the b bus are displayed at the a bus hh x* x l l l the data at the b bus are displayed at the a bus. the data of the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. hh x*xxh qn x the data stored to the internal flip-flops are displayed at the a bus x* x h l l the data at the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the a bus. hh
m74hct646 3/13 logic diagram timing chart
m74hct646 4/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied (*) 500mw at 65 c; derate to 300mw by 10mw/ c from 65 c to 85 c recommended operating conditions symbol parameter value unit v cc supply voltage -0.5 to +7 v v i dc input voltage -0.5 to v cc + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current 20 ma i ok dc output diode current 20 ma i o dc output current 35 ma i cc or i gnd dc v cc or ground current 70 ma p d power dissipation 500(*) mw t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 4.5 to 5.5 v v i input voltage 0 to v cc v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c t r , t f input rise and fall time (v cc = 4.5 to 5.5v) 0 to 500 ns
m74hct646 5/13 dc specifications symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 4.5 to 5.5 2.0 2.0 2.0 v v il low level input voltage 4.5 to 5.5 0.8 0.8 0.8 v v oh high level output voltage 4.5 i o =-20 m a 4.4 4.5 4.4 4.4 v i o =-6.0 ma 4.18 4.31 4.13 4.10 v ol low level output voltage 4.5 i o =20 m a 0.0 0.1 0.1 0.1 v i o =6.0 ma 0.17 0.26 0.33 0.40 i i input leakage current 5.5 v i = v cc or gnd 0.1 1 1 m a i oz high impedance output leakage current 5.5 v i = v ih or v il v o = v cc or gnd 0.5 5 10 m a i cc quiescent supply current 5.5 v i = v cc or gnd 44080 m a d i cc additional worst case supply current 5.5 per input pin v i = 0.5v or v i = 2.4v other inputs at v cc or gnd i o = 0 2.0 2.9 3.0 ma
m74hct646 6/13 ac electrical characteristics (c l = 50 pf, input t r = t f = 6ns) capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8 (per bit) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t tlh t thl output transition time 4.5 50 7 12 15 19 ns t plh t phl propagation delay time 4.5 50 20 30 38 48 ns 150 25 38 48 60 t plh t phl propagation delay time(clock-a,b) 4.5 50 29 44 55 65 ns 150 34 52 65 75 t plh t phl propagation delay time (select - a,b) 4.5 50 24 34 43 53 ns 150 29 42 53 65 t pzl t pzh high impedance output enable time (g , dir) 4.5 50 r l = 1 k w 26 38 48 60 ns 150 r l = 1 k w 31 46 58 70 t plz t phz high impedance output disable time (g , dir) 4.5 50 r l = 1 k w 26 35 44 55 ns f max maximum clock frequency 4.5 50 31 55 25 20 mhz t w(h) t w(l) minimum pulse width 4.5 50 8 15 19 ns t s minimum set-up time 4.5 50 3 10 13 13 ns t h minimum hold time 4.5 50 5 5 5 ns symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 5101010pf c i/o bus terminal capacitance 13 pf c pd power dissipation capacitance (note 1) 40 pf
m74hct646 7/13 test circuit c l = 50pf/150pf or equivalent (includes jig and probe capacitance) r 1 = 1k w or equivalent r t = z out of pulse generator (typically 50 w ) waveform 1: propagation delay time (f=1mhz; 50% duty cycle) test switch t plh , t phl open t pzl , t plz v cc t pzh , t phz gnd
m74hct646 8/13 waveform 2 : clock ab, ba minimum pulse width, propagation delay time (f=1mhz; 50% duty cycle) waveform 3: a, b to clock minimum setup and hold time (f=1mhz; 50% duty cycle)
m74hct646 9/13 waveform 4 : output enable and disable time (f=1mhz; 50% duty cycle) waveform 5: output enable and disable time (f=1mhz; 50% duty cycle)
m74hct646 10/13 dim. mm. inch min. typ max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.500 d 32.2 1.268 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 27.94 1.100 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 plastic dip-24 (0.25) mechanical data p043a
m74hct646 11/13 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s8 (max.) so-24 mechanical data po13t f c l e a1 b1 a e d e3 b 24 13 112 c1 s a2
m74hct646 12/13 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 6.25 6.5 0.246 0.256 e1 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.50 0.70 0.020 0.028 tssop24 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7047476a
m74hct646 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 13/13

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